The present disclosure relates to fin-shaped field effect transistors (finFETs), and more specifically, to use of a semiconductor fin loop for a diffusion break.
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (with both n-type MOS (NMOS) and p-type MOS (PMOS) transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode together may sometimes be referred to as the gate stack structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epitaxial (epi) semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device, or the recesses may be overfilled, thus forming raised source/drain regions. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs can be scaled down significantly (i.e., channel length decreased), which can improve the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected (e.g., by larger leakage current) by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called finFET device has a three-dimensional (3D) structure. FIG. 1A is a side view of an illustrative prior art finFET semiconductor device 10 that is formed above a semiconductor substrate 12. In this example, finFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18, and a gate cap 20. Gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal, metal nitride, and/or polysilicon) that serve as the gate electrode and work-function layers (for setting threshold voltage (Vt)) for device 10. Fins 14 have a three-dimensional configuration. The portions of fins 14 covered by gate structure 16 is the channel region of finFET device 10, which is also in a three-dimensional configuration. An isolation structure 22 is formed between fins 14. In a conventional process flow, the portions of fins 14 that are positioned outside of spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size (i.e., width and height) or even merged together by performing one or more epitaxial growth processes. The process of increasing the size of fins 14 in the source/drain regions of device 10 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions.
A particular fin 14 may be used to fabricate multiple devices. FIG. 1B illustrates a cross-sectional view of finFET device 10 along the length of one fin 14 prior to the formation of any gate structures 16. One or more diffusion breaks 30, 32 are formed along the axial length of fin 14 to define separate fin portions by removing a portion of fin 14 and replacing it with a dielectric material. The strength of the isolation provided by diffusion break 30, 32 depends on its size. A diffusion break having a wider lateral width (in the current transport direction, or gate length (GL) direction of the completed devices) corresponding to the lateral width of two adjacent gate structures 16 (later formed) is referred to as a double diffusion break (DDB) 30, and a diffusion break having a lateral width corresponding to the lateral width of one gate structure 16 is referred to as a single diffusion break (SDB) 32. The specific process for forming the single diffusion break may intentionally gouge fin 14 and define recesses 34 (for reasons described herein). As illustrated, each diffusion break includes an isolation region made of a dielectric.
FIG. 1C illustrates device 10 after a plurality of processes were performed to define a plurality of gate structures 16, with cap layers 20, and sidewall spacers 18 above fin 14. A gate structure formed over SDB 32 is often referred to as a dummy gate 36, since it is not over active semiconductor material but dielectric. Spacers 38 surround dummy gate 36.
FIGS. 1D-1F show processes to enlarge source/drain regions in fin 14. FIG. 1D illustrates device 10 after a self-aligned etch process was performed to recess fin 14 using the gate structures 16 and spacers 18 as an etch mask to define recesses 40, 42 in fin 14. Because of the fin gouging, recesses 40 adjacent the single diffusion break 32 are deeper than the other recesses 40. FIGS. 1E-1F illustrate device 10 after an epitaxial growth process was performed to define epitaxial regions 62, 70 (FIG. 1E) in recesses 40, 42 (FIG. 1D) for source and drain 70, 72 (FIG. 1F) of device 10, respectively. In some instances, source/drain 70, 72 are raised compared to a top surface of fin 14. Ideally, after the recessing, some semiconductor material remains under dummy gate 36 and spacers 38 thereof to allow formation of well-defined sources/drains 70, 72. As shown in FIG. 1E, however, where some, but too little, semiconductor material of fin 14 remains under edges of dummy gate 36 and spacers 38 thereof, source/drain 70, 72 of device 10 suffer from poor epi growth under the edges and leakage between source/drain 70, 72 through dummy gate 36. In addition, as shown in FIG. 1F, during formation, dielectric for SDB 32 may be larger than a width of dummy gate 36 and spacers 38. In this case, the semiconductor material of fin 14 may not remain present under dummy gate 36 and spacers 38 thereof, which prevents epitaxy (epi) growth for source/drain 70, 72 from growing under dummy gate 36 and spacers 38. Here, source/drain 70, 72 grow in a poor manner, resulting in asymmetric growth without ideal facets. This situation is especially problematic when trying to land source and drain contacts on epi of source/drain 70, 72, e.g., because not enough surface area is generated of the source or drain. In this case, the contact area will not be positioned as high as desired, which may result in current crowding issues. Further, the structure of device 10 still provides a potential leakage path through dummy gate 36.
One approach to attempt to address this concern includes employing a T-shaped isolation trench for SDB 32 (i.e. the slight recess 34 in FIG. 1B or 1C, and later filled with dielectrics 32). However, this approach creates a number of additional challenges such as asymmetric source and drains that are non-communicative, or the isolation trench blocking epitaxy growth that forms the source/drain. Another approach attempts to form the SDB after formation of the active finFETs, which adds complexity and numerous processing steps. In either approach, one is likely to create a poorly functioning or inoperative device.